diff --git a/__version__.py b/__version__.py
index a0f5d6f..94a2786 100644
--- a/__version__.py
+++ b/__version__.py
@@ -1,2 +1,2 @@
 VERSION = 'v5.5.0'
-PATCH = 'UVR_Patch_12_18_22_6_41'
+PATCH = 'UVR_Patch_12_21_22_12_41'
\ No newline at end of file
diff --git a/separate.py b/separate.py
index 2cf43ca..31b4224 100644
--- a/separate.py
+++ b/separate.py
@@ -155,6 +155,7 @@ class SeperateAttributes:
             self.crop_size = model_data.crop_size
             self.window_size = model_data.window_size
             self.input_high_end_h = None
+            self.post_process_threshold = model_data.post_process_threshold
             self.aggressiveness = {'value': model_data.aggression_setting, 
                                    'split_bin': self.mp.param['band'][1]['crop_stop'], 
                                    'aggr_correction': self.mp.param.get('aggr_correction')}
@@ -607,9 +608,11 @@ class SeperateVR(SeperateAttributes):
             #print('ARC SIZE: ', nn_architecture)
 
             if nn_architecture in vr_5_1_models:
+                print('NEW: ', nn_architecture)
                 model = nets_new.CascadedNet(self.mp.param['bins'] * 2, nn_architecture)
                 inference = self.inference_vr_new
             else:
+                print('OLD: ', nn_architecture)
                 model = nets.determine_model_capacity(self.mp.param['bins'] * 2, nn_architecture)
                 inference = self.inference_vr
 
@@ -739,7 +742,7 @@ class SeperateVR(SeperateAttributes):
                    
         if self.is_post_process:
             pred_inv = np.clip(X_mag - pred, 0, np.inf)
-            pred = spec_utils.mask_silence(pred, pred_inv)
+            pred = spec_utils.mask_silence(pred, pred_inv, thres=self.post_process_threshold)
             
         y_spec = pred * X_phase
         v_spec = X_spec - y_spec
@@ -850,6 +853,8 @@ def process_secondary_model(secondary_model: ModelData, process_data, main_model
     
 def gather_sources(primary_stem_name, secondary_stem_name, secondary_sources: dict):
     
+    print(primary_stem_name, secondary_stem_name)
+    
     source_primary = False
     source_secondary = False